An efficient serialized hardware implementation of the ASCON algorithm
Hasan Abdel Aziz Mohamed, Mariam Taher, Hossam Moetaz Shousha, Ziad Mohsen, Mostafa M. Abdelrazik, Yehea Ismail, Ahmed Saeed · 2026
Read An efficient serialized hardware implementation of the ASCON algorithm by Hasan Abdel Aziz Mohamed, Mariam Taher, Hossam Moetaz Shousha, Ziad Mohsen, Mostafa M. Abdelrazik, Yehea Ismail, Ahmed Saeed (2026) in the Tower of Babel, a free online library of public-domain works preserved in clean, searchable text. No sign-up. The full text is served as a plain-text file at a predictable URL, where text is present: https://antarctic-labs.com/tower-of-babel/PMC13396216.txt.
Description
Hasan Abdel Aziz Mohamed and co-authors built a compact hardware version of ASCON, the cipher chosen for lightweight cryptography, and describe it in a 2026 paper. Small internet-connected devices need strong encryption but have little power or chip space to spare.
Their design processes data in a serial stream rather than in wide parallel blocks, which trims the logic needed. On a low-power Lattice iCE40 chip it reached a top speed of 228.8 megahertz using only 582 lookup tables and 418 flip-flops, and drew 2.28 milliwatts at a lower test speed. The chip runs ASCON-128 in its authenticated mode, which both hides data and proves it was not altered.
Catalog record
| CREATOR | Hasan Abdel Aziz Mohamed, Mariam Taher, Hossam Moetaz Shousha, Ziad Mohsen, Mostafa M. Abdelrazik, Yehea Ismail, Ahmed Saeed |
|---|---|
| YEAR | 2026 |
| COLLECTION | PAPERS |
| FORMAT | TXT |
| FILE SIZE | 57 KB |
| LICENSE | https://creativecommons.org/licenses/by/4.0 |
| RIGHTS | CC BY |
| SOURCE | Europe PMC |