A scalable security co-processor design for IoT applications
Mohamed Niazy, Haytham Azmi, Mervat M. A. Mahmoud · 2026
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Description
A RISC-V security chip add-on for internet devices is designed by Mohamed Niazy and colleagues in 2026. Connected devices face growing, smarter cyber attacks with tight power budgets. Their co-processor speeds cipher work while staying flexible across algorithms.
A generic port lets cipher blocks plug in without changing core instructions. Blocks run in parallel, and memory moves bypass the main pipeline for speed. The design was built and verified on a Xilinx FPGA board. Encryption throughput reached multi-gigabit rates for the AES block tested. Hashing ran slower, as expected for that algorithm class. Efficiency suits small connected devices.
Catalog record
| CREATOR | Mohamed Niazy, Haytham Azmi, Mervat M. A. Mahmoud |
|---|---|
| YEAR | 2026 |
| COLLECTION | PAPERS |
| FORMAT | TXT |
| FILE SIZE | 100964 |
| LICENSE | https://creativecommons.org/licenses/by/4.0 |
| RIGHTS | CC BY |
| SOURCE | Europe PMC |