Low power and high-speed quadrate node upset tolerant latch design using CNTFET
Shaik Asiya, Satheesh Kumar S · 2025
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Description
Shaik Asiya and Satheesh Kumar S present a chip latch built to shrug off radiation upsets while using little power, in a 2025 paper. As circuits shrink, stray charged particles hitting a chip can flip stored bits, and one strike can disturb several nodes at once. Older hardening tricks add bulk and slow things down. The pair instead build their latch from carbon nanotube transistors, a newer device type.
Their design links three interlocked cells in a delta pattern, giving spare nodes so a multi-node upset cannot flip the stored value. In simulations at one volt, the latch drew about 4.4 microwatts with very low delay, beating rival hardened latches on power and speed measures at the same tolerance level.
Catalog record
| CREATOR | Shaik Asiya, Satheesh Kumar S |
|---|---|
| YEAR | 2025 |
| COLLECTION | PAPERS |
| FORMAT | TXT |
| FILE SIZE | 46 KB |
| VERSION | 1.0 |
| LICENSE | CC BY 4.0 |
| RIGHTS | CC BY |
| SOURCE | Europe PMC |